1. Technical Field
The present invention relates to a substrate, a manufacturing method thereof, a method for manufacturing a semiconductor device.
2. Related Art
There are two types of a semiconductor package, one is a peripheral type in which an external terminal is arranged on the periphery of a package, and the other is an area type in which an external terminal is disposed under a package. Referring to FIGS. 26A through 26C, the peripheral type package is typified by Dual Inline Package (DIP), Small Outline Package (SOP) and Quad Flat Package (QFP). Referring to FIG. 26D, in the peripheral type package, an integrated circuit (IC) element 210 is mounted on a chip mounting part called a die pad 201. An electrode on the IC element 210 and a lead 203 of a lead frame are coupled each other through a gold wire and the like. All areas other than a peripheral area of the lead 203 are sealed with resin and the peripheral type package is completed. The lead 203 is provided in the plural number, the lead that is disposed inside the resin package is called an inner terminal and the lead that is disposed outside the resin package is called an external terminal.
Referring to FIGS. 27A, 27B and FIGS. 28A, 28B, the area type package is typified by Ball Grid Array (BGA). In the area type package, the IC element 210 is mounted on a substrate 211, the substrate 211 and the IC element 210 are electrically coupled each other through a gold wire, solder or a gold bump, and the IC element 210 and other parts are sealed with resin. Referring to FIGS. 27A and 27B, the package in which the substrate 211 and the IC element 210 are coupled with a gold wire 213 is called as a gold wire type BGA.
Referring to FIGS. 28A and 28B, the package in which the substrate 211 and the IC element 210 are coupled through a bump 223 is called as a bump type BGA. There are some bump type BGAs with which resin sealing is not performed as illustrated in FIGS. 28A and 28B. Referring to FIGS. 27A through 28B, the external terminal of the area type is not a lead but an electrode (or a solder ball) 225 that is mounted on a lower face of the substrate 211.
Referring to FIGS. 29A through 29I, another type of the package has been proposed in recent years. A column shaped terminal 233 and a die pad 235 are formed on a metal plate 231 by electroplating, the IC element 210 is mounted on the die pad 235, the IC element 210 and the terminal 233 are coupled with the gold wire 213, the parts are sealed with resin, and the metal plate 231 is removed from a resin mold part 236. The remaining is diced into each piece of package in order to make it as a completed product.
More specifically, referring to FIGS. 29A and 29B, a resist solution is firstly applied onto the metal plate 231, and a resist pattern 237 is formed by conducting an exposure-development process. Referring to FIG. 29C, cupper or the like is deposited on the metal plate 231 which is exposed from the resist pattern 237 by electroplating so as to form the column shaped terminal 233 and the die pad 235. The resist pattern is then removed as shown in FIG. 29D. Referring to FIG. 29E, the IC element 210 is mounted on the die pad 235 that has been formed by the electroplating, and wire-bonding is conducted. Subsequently the IC element 210, the gold wire 213 and the like are sealed with resin as shown in FIG. 29F. Referring to FIG. 29G, the metal plate 231 is removed from the resin mold part 236. Finally the resin mold part 236 is diced into each piece of the completed product as shown in FIGS. 29H and 29I and the package is completed.
JP-A-2-240940 is a first example of related art. The first example discloses how to fabricate the peripheral type package. One face of a support part of a plate-shaped lead frame is half-etched, and an IC element is mounted on a die pad of the lead frame. Wire-bonding and resin sealing are subsequently performed, the other face of the support part whose face has been half-etched is then grinded so as to remove the support part, and the peripheral type package is completed. JP-A-2004-281486 is a second example of the related art. The second example discloses a technique to increase versatility of the area type package by arranging wiring lines when it is viewed in plan. JP-A-2006-108343 is a third example of the related art. The third example discloses a technique to dice the sealing resin and the like.
According to the hitherto known technique, any of the peripheral type package, the area type package, the package that is described above with reference to FIGS. 29A through 29I, and the package disclosed in the first example require a die pad or a substrate such as an interposer for mounting an IC element. This means that a lead frame, a substrate or a photo-mask (for forming a post) have to be customized depending on the size of the IC element and the number of external outputs (in other words, the number of the leads or balls) from the IC element. Especially in case of manufacturing diversified products in small quantities, a wide variety of lead frames, substrates and photo-masks are needed depending on the products, and this makes it difficult to reduce a manufacturing cost.
The second example realizes the area type package that can accommodate to a large to small sized chip by arranging wiring lines in a radial pattern extending outward from the center of a substrate. However, according to this technique, pad terminals of the IC element have to be arranged such that they are overlapped with the wiring lines that extend in the radial pattern outward from the center of the substrate when it is viewed in plan. Therefore design freedom in the pad arrangement is limited. In other words, the versatility of the package is increased but constraints on the IC element also increase.